C5NPD0-DS datasheet(69/100 Pages) FREESCALE

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Power Sequencing

V 04

Each control input pin has a capacitance associated with it. The capacitance at the control

input is due to the package and the input circuitry connected to the pin. Capacitance is

based on these conditions: T

A = 25°C; VDD33 = 3.3V; f = 1MHz. Table 37 provides

capacitance data.

Power Sequencing

The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated

for periods up to one second, as is typical during power sequencing, as long as:

• The VDD is not clamped to ground or some other low voltage.

• The number of power cycling events averages to less than once per day over the

lifetime of the product.

It is intended that the VDD and VDD33 rail be sequenced to their final value together for

most applications.

It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running

or begin running during power sequencing to propagate reset inside the C-5 NP. Figure 9

indicates the relationship between the clocks and PRSTX. There is no requirement that the

asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be

asserted within 100

µs of power initiation. Typically, reset is held low during power

initiation.

LVPECL Output Low Voltage

DD33 -1.810

DD33 -1.620

Load = 50ohm to

DD33 - 2V

LVPECL Input Current

-5

µA

CPREF

DD33 -1.38

DD33 -1.26

Single-ended LVPECL

reference

* All voltages are relative to Ground unless otherwise indicated.

Table 37 C-5 Network Processor Capacitance Data

PARAMETER

TYPICAL

MAX

UNIT

Input/Output Pins

Input Pins

Clock Pins

Table 36 C-5 Network Processor DC Characteristics (continued) (continued)

PARAMETER*

MIN

MAX

UNIT

NOTES

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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