TUSB7340 datasheet(18/117 Pages) TI1

18 / 117 page

TUSB7320, TUSB7340

SLLSE76M – MARCH 2011 – REVISED JULY 2015

www.ti.com

Programming (continued)

Figure 6. Serial-Bus Protocol - Byte Read

Figure 7 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The serial-bus

protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred.

The number of transferred data bytes is controlled by the host controller master. After each data byte, the host

controller master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a host

controller master no acknowledge (logic high) followed by a stop condition.

Figure 7. Serial-Bus Protocol - Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three

previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control bit is

asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol. This

feature allows the system designer a second serial-bus protocol option when selecting external EEPROM

devices.

7.4.1.3 Serial-Bus EEPROM Application

A serial EEPROM interface is implemented to pre-load several registers. The registers and corresponding bits

that are loaded through the EEPROM are provided in Table 4.

Table 4. EEPROM Register Loading Map

SERIAL EEPROM WORD ADDRESS

BYTE DESCRIPTION

00h

TUSB73X0 Function Indicator (00h)

01h

Number of Bytes (19h)

02h

PCI D0h, Subsystem Vendor ID, Byte 0

03h

PCI D1h, Subsystem Vendor ID, Byte 1

04h

PCI D2h, Subsystem ID, Byte 0

05h

PCI D3h, Subsystem ID, Byte 1

06h

PCI D4h, General Control 0, Byte 0

07h

PCI D5h, General Control 0, Byte 1

08h

PCI D8h, General Control 1, Byte 0

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