TUSB7340 datasheet(57/117 Pages) TI1

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TUSB7320, TUSB7340

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SLLSE76M – MARCH 2011 – REVISED JULY 2015

Table 106. De-Emphasis and Swing Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

Port 4 Deemphasis. When the PORT4_DE_OV bit is set to 1, these bits

are used to set the de-emphasis value for port 4. For details on the

27:24

PORT4_DE(1)

behavior of the swing signals refer to Table 2. For the TUSB7320 Port 4

is not present and these bits have no effect.

Port 3 Swing. When the PORT3_SWING_OV bit is set to 1 these bits are

used to set the output swing for port 3. For details on the behavior of the

23:20

PORT3_SWING(1)

swing signals refer to Table 1. For the TUSB7320 Port 3 is not present

and these bits have no effect.

Port 3 Deemphasis. When the PORT3_DE_OV bit is set to 1 these bits

are used to set the de-emphasis value for port 3. For details on the

19:16

PORT3_DE(1)

behavior of the swing signals refer to Table 2. For the TUSB7320 Port 3

is not present and these bits have no effect.

Port 2 Swing. When the PORT2_SWING_OV bit is set to 1, these bits

15:12

PORT2_SWING(1)

are used to set the output swing for port 2.For details on the behavior of

the swing signals refer to Table 1.

Port 2 Deemphasis. When the PORT2_DE_OV bit is set to 1 these bits

11:8

PORT2_DE(1)

are used to set the de-emphasis value for port 2. For details on the

behavior of the swing signals refer to Table 2.

Port 1 Swing. When the PORT1_SWING_OV bit is set to 1, these bits

7:4

PORT1_SWING(1)

are used to set the output swing for port 1. For details on the behavior of

the swing signals refer to Table 1.

Port 1 Deemphasis. When the PORT1_DE_OV bit is set to 1, these bits

3:0

PORT1_DE(1)

are used to set the de-emphasis value for port 1. For details on the

behavior of the swing signals refer to Table 2.

7.5.1.66 Equalizer Control Register

This register is used to control the equalizer settings for each of the USB 3.0 ports when the default setting is

overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express

reset (PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: E8h

Default value: 0000 0000h

Table 107. PCI Register E8h

Bit

No.

Reset

State

Bit

No.

Reset

State

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