TUSB7340 datasheet(67/117 Pages) TI1

67 / 117 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

7.5.2.10 Header Log Register

The Header Log Register stores the TLP header for the packet that lead to the most recently detected error

condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW

TLP header. Each DWORD is stored with the least significant byte representing the earliest transmitted.

PCI Express Extended Register Offset: 11Ch, 120h, 124h, 128h

Default value: 0000 0000h

Table 126. PCI Express Extended Register 11Ch, 120, 124h, and 128h

Bit

No.

Reset

State

Bit

No.

Reset

State

7.5.2.11 Device Serial Number Capability ID Register

This read-only register identifies the linked list item as the Device Serial Number Capability. This register returns

0003h when read.

PCI Express Extended Register Offset: 150h

Default value: 0003h

Table 127. Device Serial Number Capability ID Register

Bit

No.

Reset

State

7.5.2.12 Next Capability Offset/Capability Version Register

This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The upper 12

bits in this register are 000h, indicating that the Device Serial Number Capability is the last capability in the list.

The least significant four bits identify the revision of the current capability block as 1h.

PCI Express Extended Register Offset: 152h

Default value: 0001h

Table 128. Next Capability Offset/Capability Version Register

Bit

No.

Reset

State

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TUSB7340 Datasheet(PDF) 67 Page - Texas Instruments