TUSB7340 datasheet(61/117 Pages) TI1

61 / 117 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

7.5.2.3 Next Capability Offset / Capability Version Register

This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The upper 12

bits in this register shall be 150h, indicating that the Device Serial Number Capability starts at offset 150h. The

least significant four bits identify the revision of the current capability block as 2h.

PCI Express Extended Register Offset: 100h

Default value: 1502h

Table 113. PCI Express Extended Register 102h

Bit

No.

Reset

State

7.5.2.4 Uncorrectable Error Status Register

The Uncorrectable Error Status Register reports the status of individual errors as they occur. Software may clear

these bits only by writing a 1 to the desired location.

PCI Express Extended Register Offset: 104h

Default value: 0000 0000h

Table 114. PCI Express Extended Register 104h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 115. Custom PHY Transmit/Receive Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:21

RSVD

Reserved. Returns zeros when read.

Unsupported Request Error. This bit is asserted when an Unsupported

UR_ERROR(1)

rcu

Request is received.

Extended CRC Error. This bit is asserted when an Extended CRC error

ECRC_ERROR(1)

rcu

is detected.

MAL_TLP(1)

rcu

Malformed TLP. This bit is asserted when a malformed TLP is detected.

Receiver Overflow. This bit is asserted when the flow control logic

RX_OVERFLOW(1)

rcu

detects that the transmitting device has illegally exceeded the number of

credits that were issued.

Unexpected Completion. This bit is asserted when a completion packet is

UNXP_CPL(1)

rcu

received that does not correspond to an issued request.

Completer Abort. This bit is asserted when the TUSB73X0 signals a

CPL_ABORT(1)

rcu

Completer Abort.

Completion Timeout. This bit is asserted when no completion has been

CPL_TIMEOUT(1)

rcu

received for an issued request before the timeout period.

Flow Control Error. This bit is asserted when a flow control protocol error

FC_ERROR(1)

rcu

is detected either during initialization or during normal operation.

PSN_TLP(1)

rcu

Poisoned TLP. This bit is asserted when a poisoned TLP is received.

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset.

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