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TUSB7340 Datasheet(PDF) 56 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 117 page  TUSB7320, TUSB7340 SLLSE76M – MARCH 2011 – REVISED JULY 2015 www.ti.com Table 104. USB Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION USB 3.0 Port 4 Nonremovable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register 7 USB3_PORT4_NON_REM(1) rw corresponding to USB 3.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. USB 3.0 Port 3 Nonremovable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register 6 USB3_PORT3_NON_REM(1) rw corresponding to USB 3.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. USB 3.0 Port 2 Nonremovable. When this bit is set to 1, the TUSB73X0 5 USB3_PORT2_NON_REM(1) rw forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 2. USB 3.0 Port 1 Nonremovable. When this bit is set to 1, the TUSB73X0 4 USB3_PORT1_NON_REM(1) rw forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 1. USB 2.0 Port 4 Nonremovable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register 3 USB2_PORT4_NON_REM(1) rw corresponding to USB 2.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. USB 2.0 Port 3 Nonremovable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register 2 USB2_PORT3_NON_REM(1) rw corresponding to USB 2.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. USB 2.0 Port 2 Nonremovable. When this bit is set to 1, the TUSB73X0 1 USB2_PORT2_NON_REM(1) rw forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 2. USB 2.0 Port 1 Nonremovable. When this bit is set to 1, the TUSB73X0 0 USB2_PORT1_NON_REM(1) rw forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 1. 7.5.1.65 De-Emphasis and Swing Control Register This register is used to control the de-emphasis and transmit swing settings for each of the USB 3.0 ports when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: E4h Register type: Read/Write Default value: 0000 0000h Table 105. PCI Register E4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Table 106. De-Emphasis and Swing Control Register Description BIT FIELD NAME ACCESS DESCRIPTION Port 4 Swing. When the PORT4_SWING_OV bit is set to 1, these bits are used to set the output swing for port 4. For details on the behavior of 31:28 PORT4_SWING(1) rw the swing signals refer to Table 1. For the TUSB7320 Port 4 is not present and these bits have no effect. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset. 56 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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