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TUSB7340 Datasheet(PDF) 63 Page - Texas Instruments |
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TUSB7340 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 117 page  TUSB7320, TUSB7340 www.ti.com SLLSE76M – MARCH 2011 – REVISED JULY 2015 Table 117. Bit Descriptions – Uncorrectable Error Mask Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Poisoned TLP Mask. 12 PSN_TLP_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 11:5 RSVD r Reserved. Returns zeros when read. Data Link Protocol Error Mask. 4 DLL_ERROR_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 3:0 RSVD r Reserved. Returns zeros when read. 7.5.2.6 Uncorrectable Error Severity Register The Uncorrectable Error Severity Register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition will be identified as fatal. When a bit is clear, the corresponding error condition will be identified as non-fatal. PCI Express Extended Register Offset: 10Ch Register type: Read-Only, Read/Write Default value: 0026 2030h Table 118. PCI Express Extended Register 10Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 State Table 119. Bit Descriptions – Uncorrectable Error Severity Register BIT FIELD NAME ACCESS DESCRIPTION 31:23 RSVD r Reserved. Returns zeros when read. 22 RSVD r Reserved. Returns 1 when read. 21 RSVD r Reserved. Returns zeros when read. Unsupported Request Error Severity. 20 UR_ERROR_SEVR(1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Extended CRC Error Severity. 19 ECRC_ERROR_SEVR(1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Malformed TLP Severity. 18 MAL_TLP_SEVR (1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Receiver Overflow Severity. 17 RX_OVERFLOW_SEVR(1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Unexpected Completion Severity. 16 UNXP_CPL_SEVR(1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Completer Abort Severity. 15 CPL_ABORT_SEVR (1) rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Links: TUSB7320 TUSB7340 |
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