STM32U375CE datasheet(48/222 Pages) STMICROELECTRONICS

48 / 222 page

1. X = supported.

3.37

Serial peripheral interface (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to communicate with external

devices while using the specific synchronous protocol. The SPI protocol supports half-duplex, full-duplex, and

simplex synchronous, serial communication with external devices.

The interface can be configured as master or slave and can operate in multislave or multimaster configurations.

The device configured as master provides communication clock (SCK) to the slave device. The slave select (SS)

and ready (RDY) signals can be applied optionally just to setup communication with concrete slave and to assure

it handles the data flow properly. The Motorola® data format is used by default, but some other specific modes

are supported as well.

The SPI main features are:

•

Full-duplex synchronous transfers on three lines

•

Half-duplex synchronous transfer on two lines (with bidirectional data line)

•

Simplex synchronous transfers on two lines (with unidirectional data line)

•

From 4-bit up to 32-bit data size selection or fixed to multiply of 8-bit

•

Multimaster or multislave mode capability

•

Dual-clock domain, separated clock for the peripheral kernel that can be independent of APB bus clock

•

Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode

•

Protection of configuration and setting

•

Hardware or software management of SS for both master and slave

•

Adjustable minimum delays between data and between SS and data flow

•

Configurable SS signal polarity and timing, MISO x MOSI swap capability

•

Programmable clock polarity and phase

•

Programmable data order with MSB-first or LSB-first shifting

•

Programmable number of data within a transaction to control SS and CRC

•

Dedicated transmission and reception flags with interrupt capability

•

SPI Motorola® and Texas Instruments® formats support

•

Hardware CRC feature can secure communication at the end of transaction by:

–

Adding CRC value in Tx mode

–

Automatic CRC error checking for Rx mode

•

Error detection with interrupt capability in case of data overrun, CRC error, data underrun, the mode fault

and frame error at dependency on the operating mode

•

Two multiples of 8-bit embedded Rx and Tx FIFOs (FIFO size depends on instance)

•

Configurable FIFO thresholds (data packing)

•

Capability to handle data streams by system DMA controller

•

Configurable behavior at slave underrun condition (support of cascaded circular buffers)

•

Autonomous functionality in Stop modes (handling of the transaction flow and required clock distribution)

with wake-up from stop capability

•

Optional status pin RDY signalizing the slave device ready to handle the data flow.

STM32U375xx

Functional overview

DS14861 - Rev 2

page 48/222

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