STM32U375CE datasheet(9/222 Pages) STMICROELECTRONICS

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Functional overview

3.1

Arm®Cortex®-M33 core with TrustZone® and FPU

The Cortex®-M33 with TrustZone® and FPU is a highly energy-efficient processor designed for microcontrollers

and deeply embedded applications, especially those requiring efficient security.

The Cortex®-M33 processor delivers a high computational performance with low-power consumption and an

advanced response to interrupts. It features:

•

Arm® TrustZone® technology, using the Armv8_M main extension supporting secure and nonsecure states

•

MPUs (memory protection units), supporting up to 16 regions for secure and nonsecure applications

•

Configurable SAU (secure attribute unit) supporting up to eight memory regions as secure or nonsecure

•

Floating-point arithmetic functionality with support for single-precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing and a complex

algorithm execution.

The Cortex®-M33 processor supports the following bus interfaces:

•

System AHB bus:

The S-AHB (system AHB) bus interface is used for any instruction fetch and data access to the memory-

mapped SRAM, peripheral, external RAM and external device, or Vendor_SYS regions of the Armv8-M

memory map.

•

Code AHB bus:

The C-AHB (code AHB) bus interface is used for any instruction fetch and data access to the code region

of the Armv8-M memory map.

Figure 1 shows the general block diagram of the STM32U375xx devices.

3.2

Instruction cache (ICACHE)

The ICACHE is introduced on the C-AHB code bus of the Cortex®-M33 processor to improve performance when

fetching instruction (or data) from both internal and external memories.

ICACHE offers the following features:

•

Multibus interface:

–

Slave port receiving the memory requests from the Cortex®-M33 C-AHB code execution port

–

Master1 port performing refill requests to internal memories (Flash memory and SRAMs)

–

Master2 port performing refill requests to external memories (external flash memory and RAMs

through Octo-SPI interface)

–

Second slave port dedicated to ICACHE registers access

•

Close to zero wait-states instructions/data access performance:

–

0 wait-state on cache hit

–

Hit-under-miss capability, allowing to serve new processor requests while a line refill (due to a

previous cache miss) is still ongoing

–

Critical-word-first refill policy, minimizing processor stalls on cache miss

–

Hit ratio improved by two-ways set-associative architecture and pLRU-t replacement policy (pseudo-

least-recently-used, based on binary tree), algorithm with best complexity/performance balance

–

Dual master ports allowing to decouple internal and external memory traffics, on fast and slow buses,

respectively; also minimizing impact on interrupt latency

–

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

–

Performance monitoring by means of a hit counter and a miss counter

•

Extension of cacheable region beyond the code memory space, by means of address remapping logic that

allows four cacheable external regions to be defined

•

Power consumption reduced intrinsically (more accesses to cache memory rather to bigger main

memories); even improved by configuring ICACHE as direct mapped (rather than the default two-ways set-

associative mode)

•

TrustZone® security support

STM32U375xx

Functional overview

DS14861 - Rev 2

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