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STM32U375CE Datasheet(PDF) 11 Page - STMicroelectronics

Part # STM32U375CE
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 144 DMIPS, 1 MB flash memory, 256 KB SRAM, SMPS
PDF  222 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U375CE Datasheet(HTML) 11 Page - STMicroelectronics

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Table 2. Access status versus protection level and execution modes when TZEN = 0
Area
RDP level
User execution
(boot from flash memory)
Debug/boot from RAM/bootloader(1)
Read
Write
Erase
Read
Write
Erase
Flash main memory
1
Yes
Yes
Yes
No
No
No(2)
2
Yes
Yes
Yes
N/A
N/A
N/A
System memory(3)
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option bytes(4)
1
Yes
Yes(2)
N/A
Yes
Yes(2)
N/A
2
Yes
No(5)
N/A
N/A
N/A
N/A
OTP
1
Yes
Yes(6)
N/A
Yes
Yes(6)
N/A
2
Yes
Yes(6)
N/A
N/A
N/A
N/A
Backup registers
1
Yes
Yes
N/A
No
No
N/A(7)
2
Yes
Yes
N/A
N/A
N/A
N/A
SRAM2
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the flash memory interface registers and OPSTRT bit.
5. SWAP_BANK option bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
Table 3. Access status versus protection level and execution modes when TZEN = 1
Area
RDP level
User execution
(boot from flash memory)
Debug/boot from RAM/bootloader(1)
Read
Write
Erase
Read
Write
Erase
Flash main memory
1
Yes
Yes
Yes
No
No
No(4)
2
Yes
Yes
Yes
N/A
N/A
N/A
System memory(2)
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option bytes(3)
1
Yes
Yes(4)
N/A
Yes
Yes(4)
N/A
2
Yes
No(5)
N/A
N/A
N/A
N/A
OTP
1
Yes
Yes(6)
N/A
Yes
Yes(6)
N/A
2
Yes
Yes(6)
N/A
N/A
N/A
N/A
Backup registers
1
Yes
Yes
N/A
No
No
N/A(7)
2
Yes
Yes
N/A
N/A
N/A
N/A
SRAM2
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are only accessible through the flash registers interface and OPTSTRT bit.
STM32U375xx
Functional overview
DS14861 - Rev 2
page 11/222



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