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STM32U375CE Datasheet(PDF) 25 Page - STMicroelectronics

Part # STM32U375CE
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 144 DMIPS, 1 MB flash memory, 256 KB SRAM, SMPS
PDF  222 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U375CE Datasheet(HTML) 25 Page - STMicroelectronics

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Peripheral
Run Sleep
Stop 0/1
Stop 2
Stop 3
Standby
Shutdown
VBAT
-
-
-
-
-
LPTIMx (x = 1, 3, 4)
O
O
O(18)
O(18)
O(18)
O(18)
-
-
-
-
-
-
-
LPTIM2
O
O
O(18)
O(18)
-
-
-
-
-
-
-
-
-
Independent watchdog
(IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog (WWDG)
O
O
-
-
-
-
-
-
-
-
-
-
-
SysTick timer
O
O
-
-
-
-
-
-
-
-
-
-
-
Audio digital filter (ADF)
O
O
O(19)
O(19)
-
-
-
-
-
-
-
-
-
Touch sensing controller
(TSC)
O
O
-
-
-
-
-
-
-
-
-
-
-
Random number generator
(RNG)
O
O
-
-
-
-
-
-
-
-
-
-
-
Public key accelerator (PKA)
O
O
-
-
-
-
-
-
-
-
-
-
-
HASH accelerator
O
O
-
-
-
-
-
-
-
-
-
-
-
CRC calculation unit
O
O
-
-
-
-
-
-
-
-
-
-
-
GPIOs
O
O
O
O
O
O
(20)
22 pins
(20)
22 pins
(21)
22 pins
-
1. The flash banks can be configured in power-down mode. By default, they are not in power-down mode.
2. Flash can be accessed by GPDMA1 in Stop 0, Stop 1 and Stop 2 modes. ECC error interrupt or NMI wakes up from these Stop modes.
3. The SRAMs can be definitively powered off independently until the next device power on reset.
4. The SRAM clock can be gated on or off independently.
5. Subblocks of SRAM1 and SRAM2 can be powered-off to save power consumption. SRAM1 and SRAM2 can be accessed by GPDMA1 in
Stop 0, Stop 1 and Stop 2 modes.
6. Parity error interrupt or NMI wakes up from Stop mode.
7. Content of 32
‑Kbyte, 24‑Kbyte and/or 8‑Kbyte block.
8. Illegal access interrupt wakes up from Stop 0, 1, 2 modes.
9. GPDMA1 transfers are functional and autonomous in Stop 0 and 1 mode. Interrupts wake up from these Stop modes.
10. In Stop 2 mode, GPDMA1 supports only LPUART1, I2C3, LPTIM1, LPTIM3, and LPTIM4 requests. None of GPDMA1 triggers are
supported. Interrupts wake up from Stop 2 modes.
11. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16, MSIS or MSIK to be enabled. In this case,
the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
12. USART and LPUART reception and transmission is functional and autonomous in Stop mode, in asynchronous and in SPI master modes.
Interrupts wake up from Stop mode.
13. I2C reception and transmission is functional and autonomous in Stop mode. Interrupts wake up from Stop mode.
14. I3C reception and transmission, in controller and target modes, is functional and autonomous in Stop mode. Interrupts wake up from Stop
mode .
15. I3C reset pattern detection wakes up from Stop 2, Stop 3, Standby and Shutdown modes. I3C pull-ups can be applied in Stop and Standby
modes.
16. SPI reception and transmission is functional and autonomous in Stop mode. Interrupts wake up from Stop mode.
17. DAC1 (2 channels) conversion in sample and hold mode is functional and autonomous in Stop mode.
18. LPTIM is functional and autonomous in Stop mode. Interrupts wake up from Stop mode.
19. ADF is functional and autonomous in Stop mode. Interrupts wake up from Stop mode.
20. I/Os can be configured with internal pull-up, pull-down, or floating in Stop 3 and Standby mode.
21. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown
mode.
STM32U375xx
Functional overview
DS14861 - Rev 2
page 25/222



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