STM32U375CE datasheet(20/222 Pages) STMICROELECTRONICS

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Figure 4. Power-up/down sequence

0.3

VPDR

3.6

Operating mode

Power-on

Power-down

time

VDDX(1)

VDD

Invalid supply area

VDDX < VDD + 300 mV

VDDX independent from VDD

VPOR

1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.

3.8.2

Power supply supervisor

The device has an integrated brownout reset (BOR) circuitry. The BOR is active in all power modes (except

for Shutdown mode), and cannot be disabled.

During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified

VBORx threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is

above the VBORx upper limit, the device reset is released and the system can start.

Five BOR thresholds can be selected through option bytes. BOR0 provides the always enabled power-on/

powerdown functionality, independent from any other higher BOR level selection.

The devices feature an embedded programmable voltage detector (PVD) that monitors the VDD power supply and

compares it to the VPVD threshold. An interrupt can be generated when VDD drops below and/or rises above the

VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a

safe state. The PVD is enabled by software.

In addition, the devices embed a peripheral voltage monitor that compares the independent supply voltages VDDA,

VDDUSB, and VDDIO2 to ensure that the peripheral is in its functional supply range.

The devices support dynamic voltage scaling. The dynamic voltage scaling is a power management technique

that consists in increasing or decreasing the voltage used for the digital peripherals (VCORE), according to the

application performance and power consumption needs.

The regulator operates in the following ranges:

•

Range 1 (VCORE = 0.9 V) with CPU and peripherals running at up to 96 MHz

•

Range 2 (VCORE = 0.75 V) with CPU and peripherals running at up to 48 MHz

3.8.3

Reset mode

In order to improve the consumption under reset, the I/O state under and after reset is "analog state" (the I/O

Schmitt trigger is disabled). In addition, when the reset source is internal (not coming from the NRST pin), the

built-in pull-up resistor on the NRST pin is deactivated.

STM32U375xx

Functional overview

DS14861 - Rev 2

page 20/222

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