STM32U375CE datasheet(32/222 Pages) STMICROELECTRONICS

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Input clock frequency ranging from 25 MHz to the maximum frequency supported by the communication

interface (see datasheet)

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Up to 12 oversampling phases

3.20

Analog-to-digital converter (ADC)

The STM32U375xx devices embed up to 2 ADCs, ADC1 and ADC2. These are tightly coupled and can operate in

dual mode (ADC1 is master). Each ADC module consists of one 12-bit successive approximation analog-to-digital

converter. Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can be

performed in single, continuous, scan, or discontinuous mode. The result of the ADC is stored in a left-aligned or

right-aligned (default configuration) 32-bit data register.

The ADCs are mapped on the AHB bus to allow fast data handling.

The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined

high or low thresholds.

A built-in hardware oversampler allows improving analog performances while off-loading the related

computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low frequency. The main features

are:

•

High performance

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Up to 2 ADCs which can operate in dual mode

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ADC1 is connected to 15 external channels + 4 internal channels

–

ADC2 is connected to 13 external channels + 6 internal channels

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12, 10, 8 or 6-bit configurable resolution

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ADC conversion time is independent from the AHB bus clock frequency

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Faster conversion time by lowering resolution

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AHB slave bus interface to allow fast data handling

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Offset calibration support

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Channel-wise programmable sampling time

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Flexible sampling time control

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Up to 4 injected channels (analog inputs assignment to regular or injected channels is fully configurable)

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Hardware assistant to prepare the context of the injected channels to allow fast context switching

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Data alignment with in-built data coherency

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Data can be managed by DMA for regular channel conversions

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Data can be routed to MDF for post processing

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Four dedicated data registers for the injected channels

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Low-power

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Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency

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Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application

(autodelay mode)

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Allows slow bus frequency application while keeping optimum ADC performance

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Oversampler

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32-bit data register

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Oversampling ratio adjustable from 2 to 1024

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Programmable data right shift

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Data preconditioning

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Gain compensation

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Offset compensation

STM32U375xx

Functional overview

DS14861 - Rev 2

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