STM32U375CE datasheet(23/222 Pages) STMICROELECTRONICS

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Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is

switched off so that the core domain is powered off. The MSI (MSIS and MSIK) RC, the HSI16 RC and the

HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brownout reset (BOR) always remains active in Standby mode.

The state of each I/O during Standby mode can be selected by software: I/O with internal pull-up, internal

pull-down or floating.

After entering Standby mode, SRAMs and register contents are lost except for registers in the backup

domain and Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 24 Kbytes or 32 Kbytes can be

retained in Standby mode, supplied by the low-power regulator (standby with SRAM2 retention mode).

The BOR can be configured in ultra-low-power mode to further reduce power consumption during Standby

mode.

The device exits Standby mode when an external reset (NRST pin), an IWDG early wake-up event or

reset, WKUP pin event (configurable rising or falling edge), an RTC event (alarm, periodic wake-up,

timestamp), a tamper detection, or a I3C reset pattern detection occurs.

The system clock after wake-up is MSIS up to 12 MHz.

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Shutdown mode

The Shutdown mode allows the lowest power consumption. The internal regulator is switched off so that

the core domain is powered off. The HSI16, the MSI (MSIS and MSIK), the LSI, and the HSE oscillators are

also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode,

therefore the switch to backup domain is not supported.

SRAMs and register contents are lost except for registers in the backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable

rising or falling edge), or an RTC event occurs (alarm, periodic wake-up, timestamp), a tamper detection or

a I3C reset pattern detection.

The system clock after wake-up is MSIS at 12 MHz.

3.9.1

Autonomous peripherals

Several peripherals support the autonomous mode that allows it to be functional and perform DMA transfers in

Stop 0, Stop 1, and Stop 2 modes. Their interrupts wake up from Stop mode.

In Stop 0 and Stop 1 modes, the autonomous peripherals are DAC1 (2 channels), LPTIMx (x = 1 to 4),

U(S)ARTx (x = 1, 3, 4, 5), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 3), I3Cx (x = 1 to 2), ADF1 , and GPDMA1.

In Stop 2 mode, the autonomous peripherals are LPTIM1, LPTIM3, LPTIM4, LPUART1, and I2C3. If one of these

peripherals requests the AHB/APB clocks for a DMA transfer, the whole core domain is switched to Stop 1 higher

leakage mode and the clock is distributed to GPDMA1, enabled SRAMs, and peripherals in order to perform the

autonomous peripheral DMA transfer. Then the core domain automatically returns to Stop 2 lower leakage mode.

Table 9. Functionalities depending on the working mode

Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.

Peripheral

Run Sleep

Stop 0/1

Stop 2

Stop 3

Standby

Shutdown

VBAT

CPU

Flash memory up to

(1 Mbyte)

O(1)

O(2)

SRAM1 (192 Kbytes)

Y(3)

Y(4)

O(5)

SRAM2 (64 Kbytes)

Y(3)

Y(4)

O(5)

O(6)

O(5)

O(6)

O(5)

O(7)

OCTOSPI1

Backup registers

STM32U375xx

Functional overview

DS14861 - Rev 2

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