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STM32U375CE Datasheet(PDF) 49 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 49 Page - STMicroelectronics |
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49 / 222 page  Table 16. SPI features SPI feature SPI1, SPI2 (full feature set instances) SPI3 (limited feature set instance) Data size Configurable from 4 to 32-bit 8/16-bit CRC computation CRC polynomial length configurable from 5 to 33-bit CRC polynomial length 9/17-bit Size of FIFOs 16x 8-bit 8x 8-bit Number of transfered data Up to 65536 Up to 1024, no remaining data counter (CTSIZE) Autonomous in Stop 0 and Stop 1 mode with wake-up capability Yes Yes 3.38 Serial audio interfaces (SAI) The devices embed one SAI. Refer to Table 17. SAI features for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio subblocks that can be transmitters or receivers with their respective FIFO • 8-word integrated FIFOs for each audio subblock • Synchronous or asynchronous mode between the audio subblocks • Master or slave configuration independent for both audio subblocks • Clock generator for each audio block to target independent audio frequency sampling when both audio subblocks are configured in master mode • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC'97 • Up to 16 slots available with configurable size • Number of bits by frame may be configurable • PDM interface, supporting up to 4 microphone pairs • SPDIF output available if required • Frame synchronization active level configurable (offset, bit length, level) • First active bit position in the slot is configurable • LSB first or MSB first for data transfer • Mute mode • Stereo/mono audio frame capability • Communication clock strobing edge configurable (SCK) • Error flags with associated interrupts if enabled respectively – Overrun and underrun detection – Anticipated frame synchronization signal detection in Slave mode – Late frame synchronization signal detection in Slave mode – Codec not ready for the AC'97 mode in reception • Interruption sources when enabled: – Errors – FIFO requests • 2-channel DMA interface STM32U375xx Functional overview DS14861 - Rev 2 page 49/222 |
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