STM32U375CE datasheet(37/222 Pages) STMICROELECTRONICS

37 / 222 page

Note:

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O

availability.

3.27

Random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit

samples. It is composed of a live entropy source (analog) and an internal conditioning component.

The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a nondeterministic

random bit generator (NDRBG).

The RNG true random number generator has been precertified NIST SP800-90B. It has also been tested using

the German BSI statistical tests of AIS-31 (T0 to T8).

The RNG main features are the following:

•

The RNG delivers 32-bit true random numbers, produced by an analog entropy source conditioned by a

NIST SP800-90B approved conditioning stage.

•

It can be used as the entropy source to construct a nondeterministic random bit generator (NDRBG).

•

In the NIST configuration, it produces four 32-bit random samples every 412 AHB clock cycles if fAHB <

fthreshold (256 RNG clock cycles otherwise).

•

It embeds startup and NIST SP800-90B approved continuous health tests (repetition count and adaptive

proportion tests), associated with specific error management

•

It can be disabled to reduce power consumption, or enabled with an automatic low-power mode (default

configuration).

•

It has an AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only (else an AHB

bus error is generated, and the write accesses are ignored).

3.28

HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-2 family), and

the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for applications requiring

message authentication.

The hash processor computes FIPS (Federal Information Processing Standards) approved digests of length of

160, 224, 256 bits, for messages of any length less than 264 bits (for SHA-1, SHA-224 and SHA-256) or less than

2128 bits (for SHA-384, SHA-512).

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure Hash Standard

(SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital Signature Standard

(DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104, HMAC: Keyed-Hashing

for Message Authentication and Federal Information Processing Standards Publication FIPS PUB

198-1, The Keyed-Hash Message Authentication Code (HMAC)

•

Fast computation of SHA-1, SHA2-224, SHA2-256, SHA2-384, and SHA2-512

–

82 (respectively 66) clock cycles for processing one 512-bit block of data using SHA-1 (respectively

SHA-256) algorithm

–

Support for SHA-2 truncated outputs (SHA2-512/224, SHA2-512/256)

–

98 clock cycles for processing one 1024-bit block of data using either SHA2-384 or SHA2-512

algorithm

•

Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to

form the digest of the whole message:

–

Automatic 32-bit words swapping to comply with the internal little-endian representation of the input

bit string

–

Supported word swapping format: bits, bytes, half-words, and 32-bit words

•

Support for HMAC mode with all supported algorithm

•

Automatic padding to complete the input bit string to fit digest minimum block size

STM32U375xx

Functional overview

DS14861 - Rev 2

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