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STM32U375CE Datasheet(PDF) 51 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 222 page  3.40 Controller area network (FDCAN) The controller area network (CAN) subsystem consists of one CAN module, a shared message RAM memory and a configuration block. The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and transmits FIFOs. The FDCAN main features are: • Conform with CAN protocol version 2.0 part A, B, and ISO 11898-1: 2015, -4 • CAN FD with maximum 64 data bytes supported • CAN error logging • AUTOSAR and J1939 support • Improved acceptance filtering • 2 receive FIFOs of three payloads each (up to 64 bytes per payload) • Separate signaling on reception of high priority messages • Configurable transmit FIFO / queue of three payloads (up to 64 bytes per payload) • Transmit Event FIFO • Programmable loop-back test mode • Maskable module interrupts • Two clock domains: APB bus interface and CAN core kernel clock • Power-down support 3.41 USB full-speed (USB) The devices embed a USB full-speed device/host peripheral with integrated transceivers. The USB peripheral implements an interface between a full-speed USB 2.0 bus and the APB2 bus. USB suspend/resume are supported, which permits to stop the device clocks for low-power consumption. This interface requires a precise 48 MHz clock that can be generated by the internal 48 MHz oscillator (HSI48) in automatic-trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) that allows crystal less operation. The USB full-speed features are: • USB specification version 2.0 full-speed compliant • Supports both Host and Device modes • Configurable number of endpoints from 1 to 8 • Dedicated packet buffer memory (SRAM) of 2048 bytes • Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted (NRZI) encoding/ decoding and bit-stuffing • Isochronous transfers support • Double-buffered bulk/isochronous endpoint/channel support • USB Suspend/Resume operations • Frame locked clock pulse generation • USB 2.0 Link Power Management support (Device mode only) • Battery Charging Specification Revision 1.2 support (Device mode only) • USB connect / disconnect capability (controllable embedded pull-up resistor on USB_DP line) Table 19. USB features USB features(1) USB Host mode X Number of endpoints 8 Size of dedicated packet buffer memory SRAM 2048 bytes Dedicated packet buffer memory SRAM access scheme 32 bits STM32U375xx Functional overview DS14861 - Rev 2 page 51/222 |
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