STM32U375CE datasheet(30/222 Pages) STMICROELECTRONICS

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Privileged/unprivileged support:

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Support for privileged and unprivileged GPDMA transfers, independently at channel level

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Privileged-aware AHB slave port

3.16

Interrupts and events

3.16.1

Nested vectored interrupt controller (NVIC)

The devices embed an NVIC that is able to manage 16 priority levels and to handle up to 96 maskable interrupt

channels plus the 16 interrupt lines of the Cortex®-M33.

The NVIC and the processor core interface are closely coupled, enabling low-latency interrupt processing and

efficient processing of late-arriving interrupts.

The NVIC registers are banked across secure and nonsecure states.

All interrupts including the core exceptions are managed by the NVIC.

3.16.2

Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event inputs. It provides wake-

up requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU

event input. For the CPU, an additional event generation block (EVG) is needed to generate the CPU event

signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in Run modes. The EXTI also includes the

EXTI multiplexer I/O port selection.

The EXTI main features are the following:

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Up to 23 input events supported

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All event inputs allowed to wake up the system

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Configurable events (signals from I/Os or peripherals able to generate a pulse)

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Selectable active trigger edge

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Interrupt pending status register bit independent for the rising and falling edge

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Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt, and

event generation

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Software trigger possibility

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TrustZone® secure events

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The access to control and configuration bits of secure input events can be made secure and/or

privileged.

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EXTI I/O port selection

3.17

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-, or 32-bit data word

and a generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the

scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC

calculation unit helps compute a signature of the software during runtime, to be compared with a reference

signature generated at link time and stored at a given memory location.

STM32U375xx

Functional overview

DS14861 - Rev 2

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