STM32U375CE datasheet(12/222 Pages) STMICROELECTRONICS

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4. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.

5. SWAP_BANK option bit can be modified.

6. OTP can only be written once.

7. The backup registers are erased when RDP changes from level 1 to level 0.

8. All SRAMs are erased when RDP changes from level 1 to level 0.

The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:

•

Single-error detection and correction

•

Double-error detection

•

ECC fail address report

3.4.1

TrustZone® security

When the TrustZone® security is enabled through option bytes, the whole flash memory is secure after reset and

the following protections are available:

•

Nonvolatile watermark based secure flash memory area

The secure area can be accessed only in secure mode. One area per bank can be selected with a page

granularity.

•

Secure hide-protection area (HDP) and secure hide-protection extension area

It is part of the flash memory secure area and can be protected to deny access to this area by any data

read, write, and instruction fetch. For example, a software code in the secure flash memory hide-protection

area can be executed only once and deny any further access to this area until the next system reset. One

area per bank can be selected in the secure area. This area can be extended by pages that belong to the

secure area (HDP extension).

•

Volatile block based secure flash memory area

Each page can be programmed on-the-fly as secure or nonsecure.

3.4.2

Privilege protection

Each flash memory page can be programmed on the fly as privileged or unprivileged.

3.5

Embedded SRAM

The STM32U375xx devices feature 256 Kbytes of SRAM, made of several blocks that can be powered down in

Stop mode to reduce consumption:

•

SRAM1: 2 × 16 Kbytes + 5 × 32 Kbytes blocks (total 192 Kbytes)

•

SRAM2: 8 Kbytes + 24 Kbytes + 32 Kbytes blocks (total 64 Kbytes) with optional hardware parity check. In

addition, SRAM2 blocks can be retained in Standby mode.

3.5.1

TrustZone® security

When the TrustZone® security is enabled, all SRAMs are secure after reset. Both SRAMs can be programmed as

secure or nonsecure by blocks, using the MPCBB (block-based memory protection controller).

The granularity of SRAM secure block based is a page of 512 bytes.

3.5.2

Privilege protection

Both SRAMs can be programmed as privileged or unprivileged by blocks, using the MPCBB. The granularity of

SRAM privilege block based is a page of 512 bytes.

3.6

Boot modes

At startup, a BOOT0 pin, nBOOT0 and nSWBOOT0 option bits of the FLASH_OPTR register, and ADD[24:0]

option bytes of the FLASH_BOOT0R, FLASH_BOOT1R or FLASH_SBOOT0R registers are used to select the

boot memory address that includes:

•

Boot from any address in user flash memory.

•

Boot from the system memory bootloader.

•

Boot from any address in embedded SRAM.

•

Boot from RSS (root security services).

STM32U375xx

Functional overview

DS14861 - Rev 2

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