STM32U375CE datasheet(14/222 Pages) STMICROELECTRONICS

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The boot address option bytes allow any boot memory address to be programmed. However, the allowed address

space depends on the flash memory RDP level.

If the programmed boot memory address is out of the allowed memory-mapped area when RDP level is 0.5 or

more, the default boot address is forced either in secure flash memory or nonsecure flash memory, depending on

the TrustZone® security option as described in the table below.

Table 6. Boot space versus RDP protection

RDP

TZEN = 1

TZEN = 0

Any boot address

0.5

Boot address only in RSS (0x0FF8 0000) or secure flash memory:

0x0C00 0000 - 0x0C0F FFFF

Otherwise, the forced boot address is 0x0FF8 0000.

N/A

Any boot address

Boot address only in flash memory

0x0800 0000 - 0x080F FFFF

Otherwise, forced boot address is 0x0800 0000.

3.7

Global TrustZone® controller (GTZC)

GTZC is used to configure TrustZone® and privileged attributes within the full system.

The GTZC includes three different subblocks:

•

TZSC: TrustZone® security controller

This sub-block defines the secure/privileged state of slave peripherals. The TZSC informs some

peripherals (such as RCC or GPIOs) about the secure status of each securable peripheral, by sharing with

RCC and I/O logic.

•

TZIC: TrustZone® illegal access controller

This subblock gathers all security illegal access events in the system and generates a secure interrupt

towards NVIC.

•

MPCBB: Memory protection controller - block-based

This sub-block configures the internal RAM in a TrustZone®-system product having segmented SRAM

(pages of 512 bytes) with programmable-security and privileged attributes.

The GTZC main features are:

•

Three independent 32-bit AHB interfaces for TZSC, TZIC, and MPCBB

•

TZIC accessible only with secure transactions

•

Secure and nonsecure access supported for privileged/unprivileged part of TZSC and MPCBB

•

Set of registers to define product security settings:

–

Secure/privileged blocks for internal SRAMs

–

Secure/privileged access mode for securable peripherals

–

Secure/privileged access mode for securable masters

3.7.1

TrustZone® security architecture

The security architecture is based on Arm® TrustZone® with the Armv8_M main extension.

When the TrustZone® is enabled, the SAU (security attribution unit) and IDAU (implementation defined attribution

unit) define the access permissions based on secure and nonsecure state.

•

SAU: up to eight SAU configurable regions are available for security attribution.

•

IDAU: It provides a first memory partition as nonsecure or nonsecure callable attributes. It is then combined

with the results from the SAU security attribution and the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs and peripherals memory space are aliased

twice for secure and nonsecure states. However, the external memory space is not aliased.

Table 7 shows an example of typical SAU regions configuration based on IDAU regions. The user can split and

choose the secure, nonsecure, or NSC regions for external memories as needed.

STM32U375xx

Functional overview

DS14861 - Rev 2

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