STM32U375CE datasheet(42/222 Pages) STMICROELECTRONICS

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32 32-bit backup registers:

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The backup registers (TAMP_BKPxR) are implemented in the backup domain that remains powered-

on by VBAT when the VDD power is switched off.

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Up to five tamper pins for five external tamper detection events:

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Passive tampers: ultra-low-power edge or level detection with internal pull-up hardware management

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Configurable digital filter

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Nine internal tamper events to protect against transient or environmental perturbation attacks

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Each tamper can be configured in two modes:

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Confirmed mode: immediate erase of secrets on tamper detection, including backup registers erase

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Potential mode: most of the secrets erase following a tamper detection are launched by software

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Any tamper detection can generate an RTC timestamp event.

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TrustZone® support:

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Tamper secure or nonsecure configuration

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Backup registers configuration in three configurable-size areas:

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One read/write secure area

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One write secure/read nonsecure area

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One read/write nonsecure area

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Tamper configuration and backup registers privilege protection

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Monotonic counter

3.33

Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 13 for the features implementation.

The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial

I2C bus. It provides multicontroller capability, and controls all I2C bus-specific sequencing, protocol, arbitration,

and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).

The I2C peripheral supports:

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I2C-bus specification rev 3.0 compatibility:

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Target and controller modes

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Multicontroller capability

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Standard-mode (up to 100 kHz)

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Fast-mode (up to 400 kHz)

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Fast-mode Plus (up to 1 MHz)

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7-bit and 10-bit addressing mode

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Multiple 7-bit target addresses (2 addresses, 1 with configurable mask)

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Programmable setup and hold times

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Easy to use event management

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Optional clock stretching

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Software reset

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System management bus (SMBus) specification rev 3.0 compatibility:

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Hardware PEC (packet error checking) generation and verification with ACK control

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Command and data acknowledge control

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Address resolution protocol (ARP) support

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SMBus alert

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Timeouts and idle condition detection

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Power system management protocol (PMBus) specification rev 1.3 compatibility

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Independent clock: a choice of independent clock sources allowing the I2C communication speed to be

independent from the PCLK reprogramming

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Autonomous functionality in Stop modes with wake-up from Stop capability

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Programmable analog and digital noise filters

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1-byte buffer with DMA capability

STM32U375xx

Functional overview

DS14861 - Rev 2

page 42/222

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