STM32U375CE datasheet(28/222 Pages) STMICROELECTRONICS

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3.11.1

RCC TrustZone®security

When the TrustZone® security is activated by the TZEN option bit and security is enabled in the RCC, the bits

controlling the peripheral clocks and resets become TrustZone®-aware:

•

If the peripheral is securable and programmed as secure in the TZSC, the peripheral clock and reset bits

become secure.

•

If the peripheral is TrustZone®-aware, the peripheral clock and reset bits become secure as soon as at

least one function is configured as secure inside the peripheral.

A peripheral is in secure state:

•

For securable peripherals by TZSC (TrustZone® security controller), the SEC security bit corresponding to

this peripheral is set in the GTZC TZSC secure configuration registers.

•

For TrustZone®-aware peripherals, a security feature of this peripheral is enabled through its dedicated

bits.

3.12

Clock recovery system (CRS)

The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable

RC oscillator HSI48. The CRS provides a powerful means for oscillator output frequency evaluation, based on

comparison with a selectable synchronization signal. It can do automatic adjustments of oscillator trimming based

on the measured frequency error value, while keeping the possibility of a manual trimming for faster start-up

convergence.

The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the synchronization

signal can be derived from the start-of-frame (SOF) packet signalization on the USB bus. The synchronization

signal can also be derived from the LSE oscillator output, a GPIO alternate function (CRS_SYNC), or it can be

generated by user software.

3.13

General-purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions.

After reset, all GPIOs are in analog mode to reduce power consumption.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid

spurious writing to the I/Os registers.

3.13.1

GPIOs TrustZone® security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O pin is configured as

secure, its corresponding configuration bits for alternate function, mode selection, I/O data are secure against a

nonsecure access. The associated registers bit access is restricted to a secure software only. After reset, all

GPIO ports are secure.

3.14

Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all masters (CPU, GPDMA1, SDMMC1) and slave (flash memory,

RAM, OCTOSPI, SRAMs, AHB, and APB) peripherals. It also ensures a seamless and efficient operation even

when several high-speed peripherals work simultaneously.

STM32U375xx

Functional overview

DS14861 - Rev 2

page 28/222

STM32U375CE Datasheet(PDF) 28 Page - STMicroelectronics

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