STM32U375CE datasheet(31/222 Pages) STMICROELECTRONICS

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The CRC main features are the following:

•

Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

•

Alternatively, uses a fully programmable polynomial with programmable size (7, 8, 16, 32 bits)

•

Handles 8-,16-, 32-bit data size

•

Programmable CRC initial value

•

Single input/output 32-bit data register

•

Input buffer to avoid bus stall during calculation

•

CRC computation done in four AHB clock cycles (HCLK) for the 32-bit data size

•

General-purpose 8-bit register (can be used for temporary storage)

•

Reversibility options on I/O data

3.18

Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial NAND and serial NOR

flash memories, HyperRAM™ and HyperFlash™ memories, with the following functional modes:

•

Indirect mode: all the operations are performed using the OCTOSPI registers to preset commands,

addresses, data, and transfer parameters.

•

Automatic status-polling mode: the external memory status register is periodically read and an interrupt can

be generated in case of flag setting.

•

Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an

internal memory supporting read and write operation.

The OCTOSPI supports the following protocols with associated frame formats:

•

The standard frame format with the command, address, alternate byte, dummy cycles, and data phase

•

The HyperBus™ frame format

The OCTOSPI offers the following features:

•

Three functional modes: Indirect, Status-polling, and Memory-mapped

•

Read and write support in Memory-mapped mode

•

Supports for single, dual, quad, and octal communication

•

Dual memory configuration, where eight bits can be sent/received simultaneously by accessing two quad

memories in parallel.

•

SDR (single-data rate) and DTR (double-transfer rate) support

•

Data strobe support

•

Fully programmable opcode

•

Fully programmable frame format

•

Support wrapped-type access to memory in read direction

•

HyperBus™ support

•

Integrated FIFO for reception and transmission

•

8-, 16-, and 32-bit data accesses allowed

•

DMA channel for Indirect mode operations

•

DMA protocol support

•

Interrupt generation on FIFO threshold, timeout, operation complete, and access error

•

AHB interface with transaction acceptance limited to one (the interface accepts the next transfer on the

AHB bus only once the previous is completed on memory side)

The OCTOSPI registers can be configured as secure through the TZSC controller.

3.19

Delay block

The delay block (DLYB) is used to generate an output clock that is dephased from the input clock. The phase of

the output clock must be programmed by the user application. The output clock is then used to clock the data

received by another peripheral such as an SDMMC1 or OCTOSPI interface.

The delay is voltage and temperature dependent, that may require the application to reconfigure and recenter the

output clock phase with the received data.

The main features of DLYB are:

STM32U375xx

Functional overview

DS14861 - Rev 2

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