STM32U375CE datasheet(10/222 Pages) STMICROELECTRONICS

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Maintenance operation for software management of cache coherency

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Error management: detection of unexpected cacheable write access, with optional interrupt raising

3.3

Memory protection unit

The MPU (memory protection unit) is used to manage the CPU accesses to the memory and to prevent one task

to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized

into up to 16 protected areas. The MPU regions and registers are banked across secure and nonsecure states.

The MPU is especially helpful for applications where some critical or certified code must be protected against the

misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system).

If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action.

In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be

executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4

Embedded flash memory

The devices feature up to 1 Mbyte of embedded flash memory that is available for storing programs and data. The

flash memory supports up to 10 000 cycles.

A 64-bit instruction prefetch is implemented and can optionally be enabled.

The flash memory interface features:

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Dual-bank operating modes

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Read-while-write (RWW)

This allows a read operation to be performed from one bank while an erase or program operation is performed to

the other bank. The dual-bank boot is also supported. For 1-MByte devices: each bank contains 128 pages of 4

KBytes. For 512-KByte devices: each bank contains 64 pages of 4 KBytes. The flash memory also embeds 512-

byte OTP (one-time programmable) for user data.

Note:

Program, erase, and option change operations are only allowed in Range 1. An error is reported when those

operations are launched in Range 2.

The option bytes allow the configuration of flexible protections:

•

Readout protection (RDP) to protect the whole memory, has four levels of protection available (see Table 2

and Table 3).

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Level 0: no readout protection

–

Level 0.5: available only when TrustZone® is enabled

All read/write operations (if no write protection is set) from/to the nonsecure flash memory are

possible. The debug access to secure area is prohibited. Debug access to nonsecure area remains

possible.

–

Level 1: memory readout protection

The flash memory cannot be read from or written to if either the debug features are connected or the

boot in RAM or bootloader are selected. If TrustZone® is enabled, the nonsecure debug is possible

and the boot in SRAM is not possible. Regressions from Level 1 to lower levels can be protected by

password authentication.

–

Level 2: chip readout protection

The debug features (Cortex®-M33 JTAG and serial wire), the boot in RAM and the bootloader

selection are disabled. A secure secret key can be configured in the secure options to allow the

regression capability from Level 2 to Level 1. By default, this Level 2 selection is irreversible. If the

secret key was previously configured in lower RDP levels, the device enables the RDP regression

from Level 2 to Level 1 after password authentication through JTAG/SWD interface.

Note:

In order to reach the best protection level, it is recommended to activate TrustZone® and to set the

RDP Level 2 with password authentication regression enabled.

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Write protection (WRP) to protect areas against erasing and programming. Two areas per bank can be

selected with 4

‑Kbyte granularity.

STM32U375xx

Functional overview

DS14861 - Rev 2

page 10/222

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