STM32U375CE datasheet(21/222 Pages) STMICROELECTRONICS

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3.8.4

VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or an external

supercapacitor.

The VBAT pin supplies the RTC with LSE, antitamper detection (TAMP), backup registers. Five antitamper

detection pins are available in VBAT mode.

The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit

is embedded and can be activated when VDD is present.

Note:

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC/TAMP alarm/events exit the

microcontroller from the VBAT operation.

3.8.5

PWR TrustZone® security

When the TrustZone® security is activated by the TZEN option bit, some PWR register fields can be secured

against nonsecure access.

The PWR TrustZone® security allows the following features to be secured:

•

Low-power mode

•

WKUP (wake-up) pins

•

Voltage detection and monitoring

•

VBAT mode

•

I/Os pull-up/pull-down configuration

Other PWR configuration bits are secure when:

•

The system clock selection is secure in RCC: the voltage scaling configuration and the regulator booster

(BOOSTEN) are secure.

•

A GPIO is configured as secure: its corresponding bit for pull-up/pull-down configuration in Standby mode

is secure.

3.9

Low-power modes

The ultra-low-power STM32U375xx devices support several low-power modes to save power when the CPU does

not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode

that gives the best compromise between low-power consumption, short startup time, and available wake-up

sources.

Table 8. STM32U375xx low-power modes overview details the related low-power modes.

Table 8. STM32U375xx low-power modes overview

Mode name

Entry

Wake-up source

Wake-up

system clock

Effect on clocks

Voltage regulators

Sleep

(Sleep-now or

Sleep-on-exit)

WFI or return

from ISR

Any interrupt

Same as before

entering Sleep

mode

CPU clock OFF

No effect on other

clocks or analog

clock sources

Range

1, 2

WFE

Wake-up event

Stop 0

LPMS = 000 + SLEEPDEEP bit

+ WFI or return

from ISR or WFE

Any EXTI line

(configured in the

EXTI registers)

Any PWR wake-up

line (WKUP pins and

I3C reset pattern)

Specific peripherals

events/interrupts(1)

HSI16 when

STOPWUCK = 1 in

RCC_CFGR1

MSIS with the

frequency before

entering the Stop

mode, limited to

48 MHz, when

STOPWUCK = 0

All clocks OFF

except LSI and

LSE

MSIK, MSIS or

HSI16 can be

enabled

temporarily when

requested by an

autonomous

peripheral, or

forced to be kept

enabled.

Range

1, 2

Stop 1

LPMS = 001 + SLEEPDEEP bit

+ WFI or return

from ISR or WFE

Low-power

regulator (SMPS or

LDO)

Stop 2

LPMS = 010 + SLEEPDEEP bit

+ WFI or return

from ISR or WFE

STM32U375xx

Functional overview

DS14861 - Rev 2

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