TMS320VC5505 datasheet(30/135 Pages) TI

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TMS320VC5505

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

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Table 3-18. GPIO Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

General-Purpose Input/Output

External Flag Output. XF is used for signalling other processors in multiprocessor

configurations or XF can be used as a fast general-purpose output pin.

–

XF is set high by the BSET XF instruction and XF is set low by the BCLR XF

O/Z

DVDDIO

instruction or by writing to bit 13 of the ST1_55 register. At reset, the XF pin will be

high. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU

Reference Guide (literature number: SWPU073).

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CLK/

IPD

For GPIO, it is general-purpose input/output pin 0 (GP[0]).

I2S0_CLK/

L10

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[0]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CMD/

IPD

For GPIO, it is general-purpose input/output pin 1 (GP[1]).

I2S0_FS/

M11

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[1]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_D0/

IPD

For GPIO, it is general-purpose input/output pin 2 (GP[2]).

I2S0_DX/

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[2]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_D1/

IPD

For GPIO, it is general-purpose input/output pin 3 (GP[3]).

I2S0_RX/

M10

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[3]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0 and GPIO.

MMC0_D2/

IPD

For GPIO, it is general-purpose input/output pin 4 (GP[4]).

L12

I/O/Z

GP[4]

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0 and GPIO.

MMC0_D3/

IPD

For GPIO, it is general-purpose input/output pin 5 (GP[5]).

L11

I/O/Z

GP[5]

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

MMC1_CLK/

This pin is multiplexed between MMC1, I2S1, and GPIO.

IPD

I2S1_CLK/

M13

I/O/Z

For GPIO, it is general-purpose input/output pin 6 (GP[6]).

DVDDIO

GP[6]

Mux control via the SP1MODE bits in the EBSR.

This pin is multiplexed between MMC1, I2S1, and GPIO.

MMC1_CMD/

IPD

For GPIO, it is general-purpose input/output pin 7 (GP[7]).

I2S1_FS/

L14

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[7]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1, I2S1, and GPIO.

MMC1_D0/

IPD

For GPIO, it is general-purpose input/output pin 8 (GP[8]).

I2S1_DX/

M14

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[8]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1, I2S1, and GPIO.

MMC1_D1/

IPD

For GPIO, it is general-purpose input/output pin 9 (GP[9]).

I2S1_RX/

M12

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[9]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1 and GPIO.

MMC1_D2/

IPD

For GPIO, it is general-purpose input/output pin 10 (GP[10]).

K14

I/O/Z

GP[10]

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1 and GPIO.

MMC1_D3/

IPD

For GPIO, it is general-purpose input/output pin 11 (GP[11]).

L13

I/O/Z

GP[11]

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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