TMS320VC5505 datasheet(43/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

Note:

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When CLK_SEL =1, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz.

•

The on-chip Bootloader allows for DSP registers to be configured during the boot process. However,

this feature must not be used to change the output frequency of the system clock generator during the

boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The

bootloader register modification feature must not modify the Timer0 registers.

At hardware reset, all of the peripheral clocks are "off" to conserve power. After hardware reset, the DSP

boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to

determine if it can boot from that peripheral. At that time, the individual peripheral clocks will be enabled

for the query and then disabled again when the bootloader is finished with the peripheral. By the time the

bootloader releases control to the user code, all peripheral clocks will be "off" and all domains in the ICR,

except the CPU domain, will be idled.

4.4.3

DSP Resources Used By the Bootloader

The Bootloader uses SARAM block 31 for the storing of temporary data. This block of memory is reserved

during the boot process. However, after the boot process is complete, it can be used by the user

application.

Device Configuration

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TMS320VC5505 Datasheet(PDF) 43 Page - Texas Instruments