TMS320VC5505 datasheet(10/135 Pages) TI

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TMS320VC5505

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

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3.2.5

I/O Memory

The VC5505 DSP includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals

and system registers used for idle control, status monitoring and system configuration. I/O space is

separate from program/memory space and is accessed with separate instruction opcodes or via the

DMA's.

Table 3-4 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O

space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor

DMA.. For the expanded tables of each peripheral, see Section 6, Peripheral Information and Electrical

Specifications of this document.

Some DMA controllers have access to the I/O-Space memory-mapped registers of the following

peripherals registers: I2C, UART, I2S, MMC/SD, EMIF, USB, and SAR ADC .

Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is

not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the

Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).

Table 3-4. Peripheral I/O-Space Control Registers

WORD ADDRESS

PERIPHERAL

0x0000 – 0x0004

Idle Control

0x0005 – 0x000D through 0x0803 – 0x0BFF

Reserved

0x0C00 – 0x0C7F

DMA0

0x0C80 – 0x0CFF

Reserved

0x0D00 – 0x0D7F

DMA1

0x0D80 – 0x0DFF

Reserved

0x0E00 – 0x0E7F

DMA2

0x0E80 – 0x0EFF

Reserved

0x0F00 – 0x0F7F

DMA3

0x0F80 – 0x0FFF

Reserved

0x1000 – 0x10DD

EMIF

0x10EE – 0x10FF through 0x1300 – 0x17FF

Reserved

0x1800 – 0x181F

Timer0

0x1820 – 0x183F

Reserved

0x1840 – 0x185F

Timer1

0x1860 – 0x187F

Reserved

0x1880 – 0x189F

Timer2

0x1900 – 0x197F

RTC

0x1980 – 0x19FF

Reserved

0x1A00 – 0x1A6C

I2C

0x1A6D – 0x1AFF

Reserved

0x1B00 – 0x1B1F

UART

0x1B80 – 0x1BFF

Reserved

0x1C00 – 0x1CFF

System Control

0x1D00 – 0x1FFF through 0x2600 – 0x27FF

Reserved

0x2800 – 0x2840

I2S0

0x2900 – 0x2940

I2S1

0x2A00 – 0x2A40

I2S2

0x2B00 – 0x2B40

I2S3

0x2C41 – 0x2DFF

Reserved

0x2E00 – 0x2E40

LCD

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