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TMS320VC5505 Datasheet(PDF) 31 Page - Texas Instruments

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Part # TMS320VC5505
Description  Fixed-Point Digital Signal Processor
PDF  135 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5505 Datasheet(HTML) 31 Page - Texas Instruments

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TMS320VC5505
www.ti.com
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
Table 3-18. GPIO Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[2]/
IPD
For GPIO, it is general-purpose input/output pin 12 (GP[12]).
P7
I/O/Z
GP[12]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[3]/
IPD
For GPIO, it is general-purpose input/output pin 13 (GP[13]).
N7
I/O/Z
GP[13]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[4]/
IPD
For GPIO, it is general-purpose input/output pin 14 (GP[14]).
N8
I/O/Z
GP[14]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[5]/
IPD
For GPIO, it is general-purpose input/output pin 15 (GP[15]).
P9
I/O/Z
GP[15]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[6]/
IPD
For GPIO, it is general-purpose input/output pin 16 (GP[16]).
N9
I/O/Z
GP[16]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[7]/
IPD
For GPIO, it is general-purpose input/output pin 17 (GP[17]).
P10
I/O/Z
GP[17]
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D8]/
This pin is multiplexed between LCD Bridge and GPIO.
I2S2_CLK/
IPD
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
N10
I/O/Z
GP[18]/
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
SPI_CLK
enabled or disabled via the PDINHIBR3 register.
LCD_D[9]/
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
I2S2_FS/
IPD
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
P11
I/O/Z
GP[19]/
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
SPI_CS0
enabled or disabled via the PDINHIBR3 register.
LCD_D[10]/
This pin is multiplexed between LCD Bridge, I2S2, GPIOand SPI.
I2S2_RX/
IPD
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
N11
I/O/Z
GP[20]/
DVDDIO
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
SPI_RX
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 21 (GP[21]).
EM_A[15]/GP[21]
N1
I/O/Z
DVDDIO
Mux control via the A15_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 22 (GP[22]).
EM_A[16]/GP[22]
E2
I/O/Z
DVDDIO
Mux control via the A16_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 23 (GP[23]).
EM_A[17]/GP[23]
F2
I/O/Z
DVDDIO
Mux control via the A17_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 24 (GP[24]).
EM_A[18]/GP[24]
G2
I/O/Z
DVDDIO
Mux control via the A18_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 25 (GP[25]).
EM_A[19]/GP[25]
G4
I/O/Z
DVDDIO
Mux control via the A19_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 26 (GP[26]).
EM_A[20]/GP[26]
J3
I/O/Z
DVDDIO
Mux control via the A20_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
Copyright © 2009–2010, Texas Instruments Incorporated
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