CP3SP33SMSSLASHNOPB datasheet(194/407 Pages) TI1

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16-Bit counter

Reset

TSTP register

ACK slot

ACK slot and buffer 0 active

CAN bits on the bus

DS044

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Table 22-5. Highest Priority Interrupt Code (ICEN=FFFF) (continued)

CAN INTERRUPT REQUEST

IRQ

IST3

IST2

IST1

IST0

Buffer 9

Buffer 10

Buffer 11

Buffer 12

Buffer 13

Buffer 14

22.7.2 Usage Notes

The interrupt code IST3:0 can be used within the interrupt handler as a displacement to jump to the

relevant subroutine.

The CAN Interrupt Code Enable (CICEN) register is used in the CAN interrupt handler if software is

servicing all receive buffer interrupts first, followed by all transmit buffer interrupts. In this case, software

can first enable only receive buffer interrupts to be coded, then scan and service all pending interrupt

requests in the order of their priority. After processing all the receive interrupts, software changes the

CICEN register to disable all receive buffers and enable all transmit buffers, then services all pending

transmit buffer interrupt requests according to their priorities.

22.8 Time Stamp Counter

Each CAN module features a free running 16-bit timer (CTMR) incrementing every bit time recognized on

the CAN bus. The value of this timer during the ACK slot is captured into the TSTP register of a message

buffer after a successful transmission or reception of a message. Figure 22-27 shows a simplified block

diagram of the Time Stamp counter.

Figure 22-27. Time Stamp Counter

The timer can be synchronized over the CAN network by receiving or transmitting a message to or from

buffer 0. In this case, the TSTP register of buffer 0 captures the current CTMR value during the ACK slot

of a message (as above), and then the CTMR is reset to 0000b. Synchronization can be enabled or

disabled using the CGCR.TSTPEN bit.

22.9 Memory Organization

Each CAN module occupies 288 words in the memory address space. This space is organized as 15

banks of 16 words per bank (plus one 16-word reserved bank) for the message buffers and 28 words

(plus 4 reserved words) for control and status.

22.9.1 CPU Access to CAN Registers/Memory

All memory locations occupied by the message buffers are shared by the CPU and CAN modules, with

CPU access having priority over CAN access. The CAN modules and the CPU normally have single-cycle

access to this memory. However, if an access contention occurs, the access to the memory is blocked

every cycle until the contention is resolved. This access arbitration is transparent to software.

194

Dual CAN Interfaces

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