R5F10WMDA datasheet(35/126 Pages) RENESAS

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RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 35 of 123

(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA =

−40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

2.7 V

≤ VDD ≤ 5.5 V

167Note 1

500Note 1

1000Note 1

2.4 V

≤ VDD ≤ 5.5 V

250Note 1

500Note 1

1000Note 1

1.8 V

≤ VDD ≤ 5.5 V

−

500Note 1

1000Note 1

1.6 V

≤ VDD ≤ 5.5 V

−

1000Note 1

SCKp high-/low-level

width

tKH1,

tKL1

4.0 V

≤ VDD ≤ 5.5 V

tKCY1/2

−12

tKCY1/2

−50

tKCY1/2

−50

2.7 V

≤ VDD ≤ 5.5 V

tKCY1/2

−18

tKCY1/2

−50

tKCY1/2

−50

2.4 V

≤ VDD ≤ 5.5 V

tKCY1/2

−38

tKCY1/2

−50

tKCY1/2

−50

1.8 V

≤ VDD ≤ 5.5 V

−

tKCY1/2

−50

tKCY1/2

−50

1.6 V

≤ VDD ≤ 5.5 V

−

tKCY1/2

−100

SIp setup time

(to SCKp

↑)Note 2

tSIK1

2.7 V

≤ VDD ≤ 5.5 V

110

2.4 V

≤ VDD ≤ 5.5 V

110

1.8 V

≤ VDD ≤ 5.5 V

−

110

1.8 V

≤ VDD ≤ 5.5 V

−

220

SIp hold time

(from SCKp

↑)Note 3

tKSI1

2.4 V

≤ VDD ≤ 5.5 V

1.8 V

≤ VDD ≤ 5.5 V

−

1.6 V

≤ VDD ≤ 5.5 V

−

Delay time from

SCKp

↓ to

SOp outputNote 4

tKSO1

C = 30 pFNote 5

2.4 V

≤ VDD ≤ 5.5 V

1.8 V

≤ VDD ≤ 5.5 V

−

1.6 V

≤ VDD ≤ 5.5 V

−

Notes 1.

The value must also be equal to or more than 2/fCLK for CSI00 and equal to or more than 4/fCLK for CSI10.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin

by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks 1.

p: CSI number (p = 00, 10), m: Unit number (m = 0), n: Channel number (n = 0, 2),

g: PIM and POM numbers (g = 0, 1)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 02))

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