R5F10WMDA datasheet(40/126 Pages) RENESAS

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RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 40 of 123

(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)

(TA =

−40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer rate

Reception

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

fMCK/6Note

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 3

4.0

1.3

0.6

Mbps

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

fMCK/6Note

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 3

4.0

1.3

0.6

Mbps

1.8 V (2.4 VNote 4)

≤ VDD < 3.3

1.6 V

≤ Vb ≤ 2.0 V

fMCK/6

Note s1, 2

fMCK/6

Notes 1, 2

fMCK/6

Notes 1, 2

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLKNote 3

4.0

1.3

0.6

Mbps

Notes 1.

Transfer rate in SNOOZE mode is 4800 bps only.

Use it with VDD

≥ Vb.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

LS (low-speed main) mode:

8 MHz (1.8 V

≤ VDD ≤ 5.5 V)

LV (low-voltage main) mode:

4 MHz (1.6 V

≤ VDD ≤ 5.5 V)

Condition in the HS (high-speed main) mode

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for

the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).

For

VIH and VIL, see the DC characteristics with TTL input buffer selected.

Remarks 1.

Vb[V]: Communication line voltage

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13)

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