R5F10WMDA datasheet(47/126 Pages) RENESAS

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RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 47 of 123

(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2)

(TA =

−40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SIp setup time

(to SCKp

↓)Note 4

tSIK1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

110

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

110

1.8 V (2.4 VNote 1)

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 k

110

SIp hold time

(from SCKp

↓)Note

tKSI1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

1.8 V (2.4 VNote 1)

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 k

Delay time from

SCKp

↑ to

SOp outputNote 4

tKSO1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

1.8 V (2.4 VNote 1)

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote 2,

Cb = 30 pF, Rb = 5.5 k

Notes 1.

Condition in HS (high-speed main) mode

Use it with VDD

≥ Vb.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the

SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g

(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

CSI mode connection diagram (during communication at different potential)

SCKp

SOp

SCK

User device

SIp

RL78

microcontroller

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