R5F10WMDA datasheet(87/126 Pages) RENESAS

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RL78/L13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA =

−40 to +105°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 87 of 123

3.4 AC Characteristics

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Instruction cycle (minimum

instruction execution time)

TCY

Main system

clock (fMAIN)

operation

HS (high-speed

main) mode

2.7 V

≤ VDD ≤ 5.5 V

0.0417

μs

2.4 V

≤ VDD < 2.7 V

0.0625

μs

Subsystem clock (fSUB)

operation

2.4 V

≤ VDD ≤ 5.5 V

28.5

30.5

31.3

μs

In the self

programming

mode

HS (high-speed

main) mode

2.7 V

≤ VDD ≤ 5.5 V

0.0417

μs

2.4 V

≤ VDD < 2.7 V

0.0625

μs

External system clock

frequency

fEX

2.7 V

≤ VDD ≤ 5.5 V

1.0

20.0

MHz

2.4 V

≤ VDD < 2.7 V

1.0

16.0

MHz

fEXS

kHz

External system clock input

high-level width, low-level

width

tEXH, tEXL

2.7 V

≤ VDD ≤ 5.5 V

2.4 V

≤ VDD < 2.7 V

tEXHS, tEXLS

13.7

μs

TI00 to TI07 input high-level

width, low-level width

tTIH, tTIL

1/fMCK+

TO00 to TO07, TKBO00Note,

TKBO01-0 to TKBO01-2Note

output frequency

fTO

HS (high-speed main)

mode

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

2.4 V

≤ VDD < 2.7 V

MHz

PCLBUZ0, PCLBUZ1 output

frequency

fPCL

HS (high-speed main)

mode

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

2.4 V

≤ VDD < 2.7 V

MHz

Interrupt input high-level

width, low-level width

tINTH, tINTL

INTP0 to INTP7

2.4 V

≤ VDD ≤ 5.5 V

μs

Key interrupt input high-level

width, low-level width

tKRH, tKRL

KR0 to KR7

2.4 V

≤ VDD ≤ 5.5 V

250

IH-PWM output restart input

high-level width

tIHR

INTP0 to INTP7

fCLK

TMKB2 forced output stop

input high-level width

tIHR

INTP0 to INTP2

fCLK

RESET low-level width

tRSL

μs

(Note and Remark are listed on the next page.)

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