R5F10WMDA datasheet(42/126 Pages) RENESAS

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RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 42 of 123

Notes 6.

The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum

transfer rate.

Expression for calculating the transfer rate when 1.8 V (2.4 VNote 8)

≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V

Maximum transfer rate =

[bps]

{

−Cb × Rb × ln (1 −

1.5

Vb )} × 3

Transfer rate

× 2 −

{

−Cb × Rb × ln (1 −

1.5

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

Condition in the HS (high-speed main) mode

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the

TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).

For VIH

and VIL, see the DC characteristics with TTL input buffer selected.

UART mode connection diagram (during communication at different potential)

RL78

microcontroller

TxDq

RxDq

User device

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