R5F10WMDA datasheet(85/126 Pages) RENESAS

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RL78/L13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA =

−40 to +105°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 85 of 123

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Low-speed on-

chip oscillator

operating current

IFILNote 1

0.20

μA

RTC2 operating

current

IRTCNotes 1, 2, 3 fSUB = 32.768 kHz

0.02

μA

12-bit interval

timer operating

current

ITMKANotes 1, 2, 4

0.04

μA

Watchdog timer

operating current

IWDTNotes 1, 2, 5

fIL = 15 kHz

0.22

μA

A/D converter

operating current

IADCNotes 1, 6

When conversion

at maximum speed

Normal mode, AVREFP = VDD = 5.0 V

1.3

1.7

Low voltage mode, AVREFP = VDD = 3.0 V

0.5

0.7

A/D converter

reference

voltage current

IADREFNote 1

75.0

μA

Temperature

sensor operating

current

ITMPSNote 1

75.0

μA

LVD operating

current

ILVDNotes 1, 7

0.08

μA

Comparator

operating current

ICMPNotes 1, 11

VDD = 5.0 V,

Regulator output

voltage = 2.1 V

Window mode

12.5

μA

Comparator high-speed mode

6.5

μA

Comparator low-speed mode

1.7

μA

VDD = 5.0 V,

Regulator output

voltage = 1.8 V

Window mode

8.0

μA

Comparator high-speed mode

4.0

μA

Comparator low-speed mode

1.3

μA

Self-

programming

operating current

IFSPNotes 1, 9

2.00

12.20

BGO operating

current

IBGONotes 1, 8

2.00

12.20

SNOOZE

operating current

ISNOZNote 1

ADC operation

While the mode is shiftingNote 10

0.50

0.60

During A/D conversion, in low voltage

mode, AVREFP = VDD = 3.0 V

1.20

1.44

CSI/UART operation

0.70

0.84

LCD operating

current

ILCD1Notes 1, 12,

External resistance

division method

fLCD = fSUB

LCD clock

= 128 Hz

1/3 bias,

four time

slices

VDD = 5.0 V,

VL4 = 5.0 V

0.04

0.20.

μA

ILCD2Note 1, 12

Internal voltage

boosting method

fLCD = fSUB

LCD clock

= 128 Hz

1/3 bias,

four time

slices

VDD = 3.0 V,

VL4 = 3.0 V

(VLCD = 04H)

0.85

2.20

μA

VDD = 5.0 V,

VL4 = 5.1 V

(VLCD = 12H)

1.55

3.70

μA

ILCD3Note 1, 12

Capacitor split

method

fLCD = fSUB

LCD clock

= 128 Hz

1/3 bias,

four time

slices

VDD = 3.0 V,

VL4 = 3.0 V

0.20

0.50

μA

(Notes and Remarks are listed on the next page.)

R5F10WMDA Datasheet(PDF) 85 Page - Renesas Technology Corp

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