R5F10WMDA datasheet(53/126 Pages) RENESAS

53 / 126 page

RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 53 of 123

(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)

(TA =

−40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Data setup time

(reception)

tSU:DAT

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK+

135Note 4

1/fMCK+

190Note 4

1/fMCK+

190Note 4

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK+

135Note 4

1/fMCK+

190Note 4

1/fMCK+

190Note 4

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK+

190Note 4

1/fMCK+

190Note 4

1/fMCK+

190Note 4

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK+

190Note 4

1/fMCK+

190Note 4

1/fMCK+

190Note 4

1.8 V (2.4 VNote 2)

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote 3,

Cb = 100 pF, Rb = 5.5 k

1/fMCK+

190Note 4

1/fMCK+

190Note 4

1/fMCK+

190Note 4

Data hold time

(transmission)

tHD:DAT

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

305

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

305

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

355

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

355

1.8 V (2.4 VNote 2)

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote 3,

Cb = 100 pF, Rb = 5.5 k

405

Notes 1.

The value must also be equal to or less than fMCK/4.

Condition in HS (high-speed main) mode

Use it with VDD

≥ Vb.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Caution

Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and

the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g

(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL

input buffer selected.

(Remarks are listed on the next page.)

R5F10WMDA Datasheet(PDF) 53 Page - Renesas Technology Corp

R5F10WMDA Datasheet(HTML) 53 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL