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STM32U375CE Datasheet(PDF) 147 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 147 Page - STMicroelectronics |
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147 / 222 page  Symbol Parameter Conditions Min Typ Max Unit RAIN(2) External input impedance Tj = 110°C Resolution = 6 bits kΩ - - 47.0 CADC Internal sample and hold capacitor - - 5 - pF tADCVREG_ STUP ADC LDO startup ready flag time - - - 25 μs tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle tOFF_CAL Offset calibration time - 123 1/fADC tLATR Trigger conversion latency WAIT = 0, AUTOFF = 0, DPD = 0, fADC = HCLK 3 ts Sampling time - 1.5 - 1499.5 tCONV Total conversion time (including sampling time) Resolution = N bits ts + N + 0.5 IDDA(ADC) ADC consumption on VDDA fs = 2.5 Msps - 360 - µA fs = 1 Msps - 180 - fs = 10 ksps - 10 - AUTOFF = 1, DPD = 0, no conversion - 9 - AUTOFF = 1, DPD = 1, no conversion - 0.1 - IDDV(ADC) ADC consumption on VREF+ fs = 2.5 Msps - 18 - fs = 1 Msps - 10.2 - fs = 10 ksps - 0.12 - AUTOFF = 1, DPD = 0, no conversion - 0.01 - AUTOFF = 1, DPD = 1, no conversion - 0.01 - 1. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA. 2. The maximum value of Rain is specified to keep leakage induced offset within the specified tolerance. The tolerance is 2 LSBs. Table 96. Maximum RAIN for 12-bit ADC BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values. The values are provided without an external capacitor. Specified by design. Not tested in production. Resolution(1) RAIN max (Ω)(2) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz 12 bits 47 276 11.5 23.5 68 288 100 306 150 336 23.5 220 377 330 442 46.5 470 526 680 650 1000 840 46.5 1500 1134 246.5 2200 1643 246.5 3300 2395 4700 3342 STM32U375xx Electrical characteristics DS14861 - Rev 2 page 147/222 |
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