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STM32U375CE Datasheet(PDF) 149 Page - STMicroelectronics |
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STM32U375CE Datasheet(HTML) 149 Page - STMicroelectronics |
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149 / 222 page ![]() Resolution(1) RAIN max (Ω)(2) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz 8 bits 33000 246.5 246.5 2995 47000 4158 6 bits 47 32 1.5 2.5 68 32 100 33 150 35 220 37 330 41 2.5 470 49 6.5 680 61 1000 79 6.5 1500 106 2200 146 11.5 3300 207 11.5 4700 286 23.5 6800 404 23.5 10000 584 46.5 22000 1250 46.5 246.5 33000 1853 246.5 47000 2607 1. The tolerance is 1 LSB 2. The maximum value of RAIN is obtained in a worst-case scenario: channel conversion in scan mode with channel i connected to VREF+ and channel i + 1 connected to VREF-. Table 97. 12-bit ADC accuracy ADC DC accuracy values are measured after internal calibration. Resolution = 12 bits, no oversampling. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. Evaluated by characterization. Not tested in production. Symbol Parameter Conditions Min Typ Max Unit ET Total unadjusted error - - ±3 ±7.5 LSB EO Offset error - - ±2 ±5.5 EG Gain error - - ±2 ±6.5 ED Differential linearity error - - -0.9/+1 -0.9/+1.5 EL Integral linearity error - - ±2 ±3.5 ENOB Effective number of bits - 9.9 10.9 - bits SINAD Signal-to-noise and distortion ratio - 61.4 67.4 - dB SNR Signal-to-noise ratio - 61.6 67.5 - THD Total harmonic distortion - - -74 -70 STM32U375xx Electrical characteristics DS14861 - Rev 2 page 149/222 |
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