301020013 datasheet(36/109 Pages) AMSOSRAM

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Dragster

Functional description

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7.5

Readout cycle

As the pixel level ADC signal is stored in an SRAM bench (LOAD_PULSE rising edge), the

digital readout is triggered by LOAD_PULSE falling edge. LOAD_PULSE signal can either be

provided externally or be generated internally (register 0x02 bit '0'). This signal must be sent

after the end of A/D conversion (rising edge of END_ADC), at the earliest possible time, based

on the state of the integration time controlling signals (RST_CVC; RST_CDS, SAMPLE) and

the programmed ADC end range. The readout is started from the most left pixel to the right. An

LVAL signal is generated to indicate valid pixel data.

Each Dragster variant has a specific number of outputs (taps).

Table 13: Dragster outputs per variant

Sensor variant

# Lines

# Outputs

Outputs

Connectors

DR2K7

A1, B1

DR2x2K7

A1, B1, C1, D1

1 & 2

DR4K7

A1, A2, B1, B2

DR4K3.5

A1, B1, C1, D1

1 & 2

DR2x4K7

A1, A2, B1, B2, C1, C2, D1, D2

1 & 2

DR6K7

A1, A2, B1, B2, E1, F1

1 & 2

DR8K7

A1, A2, B1, B2, E1, E2, F1, F2

1 & 3

DR8K3.5

A1, A2, B1, B2, C1, C2, D1, D2

1 & 2

DR2x8K7

A1, A2, B1, B2, C1, C2, D1, D2, E1, E2,

F1, F2, G1, G2, H1, H2

1 - 4

DR16K3.5

A1, A2, B1, B2, C1, C2, D1, D2, E1, E2,

F1, F2, G1, G2, H1, H2

1 - 4

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