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301020013 Datasheet(PDF) 16 Page - ams-OSRAM AG |
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301020013 Datasheet(HTML) 16 Page - ams-OSRAM AG |
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16 / 109 page  Dragster Electrical characteristics Datasheet • PUBLIC • Document Feedback DS000444 • v5-00 • 2025-Aug-29 16 / 109 / Symbol Parameter Conditions Min Typ Max Unit Characteristics for CMOS-LVTTL inputs VIL Low level input voltage -0.3 0 0.4 V VIH High level input Voltage 0.8 x VDDIO VDDIO VDDIO+0.3 V IIL Low level input leakage VI = 0 ±1 µA IIH High level input leakage VI = VDDIO ±1 µA Tslew, rising Input slew rate of rising edge 2.5 ns Tslew, falling Input slew rate of falling edge 2.5 ns TSetup, Data In Setup time for digital input signals relative to rising edge of MCLK @ MCLK pin 3 ns THold, Data In Hold time for digital input signals relative to rising edge of MCLK @ MCLK pin 3 ns TSetup, Control Signals Setup time for control signals relative to rising edge of MCLK 1 ns THold, Control Signals Hold time for control signals relative to rising edge of MCLK 6 ns TSetup, MOSI Setup time for MOSI input signals relative to rising edge of SCLK 3 ns THold, MOSI Hold time for MOSI input signals relative to rising edge of SCLK 5 ns Power consumption(5) PTotal Power consumption per 2K segment 500 mW IVDDA Current to analogue devices per 2K segment 70 mA IVDDD Current to Digital devices per 2K segment 35 mA IVDDIO Current for IO per 2K segment 40 mA (1) VDDIO < 3.0 V is not recommended for pixel clock speeds above 40 MHz and may not meet the slew rate specifications in all cases. As LCC Ceramic package has, VDDD/VDDIO/VDDESD wired internally, this situation is not applicable. (2) The input clock frequency can be lower than 1 MHz. However, the ADC conversion accuracy might be reduced. (3) The ADC can be clocked with up to 100MHz for faster conversion when using clock reduction for readout. (4) The output swing on signal pixel clock, if enabled, may be smaller at pixel clock rates above 60 MHz. (5) Typical values. |
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