R5F10WMDA datasheet(107/126 Pages) RENESAS

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RL78/L13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA =

−40 to +105°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 107 of 123

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

Data setup time (reception)

tSU:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK + 340Note 2

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK + 340Note 2

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK + 760Note 2

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK + 760Note 2

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1/fMCK + 570Note 2

Data hold time (transmission)

tHD:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

770

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

770

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1420

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1420

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V ,

Cb = 100 pF, Rb = 5.5 k

1215

Notes 1.

The value must also be equal to or less than fMCK/4.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Caution

Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and

the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g

(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL

input buffer selected.

(Remarks are listed on the next page.)

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