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R5F10WMDA Datasheet(PDF) 104 Page - Renesas Technology Corp |
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R5F10WMDA Datasheet(HTML) 104 Page - Renesas Technology Corp |
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104 / 126 page ![]() RL78/L13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 104 of 123 CSI mode connection diagram (during communication at different potential) RL78 microcontroller SCKp SOp SCK SI User device SIp SO Vb Rb <Slave> Notes 1. Transfer rate in SNOOZE mode: MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp ↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. |
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