HC705E5GRSSLASHD datasheet(20/148 Pages) NXP

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General Description

General Release Specification

MC68HC705E5 — Rev. 1.0

General Description

1.4 Mask Options

The M68HC705E5 has these four mask options which are handled with

five EPROM bits (MOR).

1. STOP instruction (enable/disable)

2. IRQ (edge-sensitive only or edge- and level-sensitive)

3. COP watchdog timer (enable/disable)

4. CPI Rate (1 second, 0.5 second, or 0.25 second)

ROM versions of this device will have these options programmed by the

factory. Refer to 13.5 Mask Option Register for additional information

NOTE:

A line over a signal name indicates an active low signal. For example,

RESET is active low.

1.5 Functional Pin Description

Figure 1-2 shows the single-chip mode pinout for the MC68HC705E5.

Refer to the following subsections for a description of the pins.

Figure 1-2. Single-Chip Mode Pinout

PA2

PA3

PA4

PA5

PA6

PA7

PC0

PC1

PC2

PC3

OSC1

OSC2

PB7/SCL

PB6/SDA

PB4/SCK

PB3/TIPL

PB2

PB1

PB0

VDD

VSS

PB5/SDIO

XFC

VDDSYN

PA0

PA1

IRQ

RESET

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 20 Page - NXP Semiconductors

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