HC705E5GRSSLASHD datasheet(82/148 Pages) NXP

82 / 148 page

Motorola Bus (M Bus) Interface

General Release Specification

MC68HC705E5 — Rev. 1.0

Motorola Bus (M Bus) Interface

11.6.3 M-Bus Control Register

The M-bus control register (MCR) provides five control bits and is

cleared upon reset.

MEN — M-Bus Enable Bit

If MEN is set, the M-bus interface system is enabled. If MEN is

cleared, the interface is reset and disabled. The MEN bit must be set

first before any bits of MCR are set.

MIEN — M-Bus Interrupt Enable Bit

If MIEN is set, an interrupt occurs provided the MIF flag in the status

MIEN is cleared, the M-bus interrupt is disabled.

MSTA — Master/Slave Mode Select Bit

Upon reset, this bit is cleared. When this bit is changed from a logic 0

to a logic 1, a start signal is generated on the bus, and master mode

is selected. When this bit is changed from a logic 1 to a logic 0, a stop

signal is generated and the operating mode changes from master to

slave.

In master mode, a bit clear immediately followed by a bit set

generates a repeated start signal (see Figure 11-1) without

generating a stop signal.

1 = Master

0 = Slave

Address:

$001A

Bit 7

654321

Bit 0

Read:

MEN

MIEN

MSTA

MTX

TXAK

MMUX

Write:

Reset:

000000

—

= Unimplemented

Figure 11-6. M-Bus Control Register (MCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 82 Page - NXP Semiconductors

HC705E5GRS/D Datasheet(HTML) 82 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL