HC705E5GRSSLASHD datasheet(34/148 Pages) NXP

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Interrupts

General Release Specification

MC68HC705E5 — Rev. 1.0

Interrupts

Unlike RESET, hardware interrupts do not cause the current instruction

execution to be halted, but are considered pending until the current

instruction is complete. The current instruction is the one already fetched

and being operated on.

When the current instruction is complete, the processor checks all

pending hardware interrupts. If interrupts are not masked (CCR I bit

clear) and the corresponding interrupt enable bit is set, the processor

proceeds with interrupt processing; otherwise, the next instruction is

fetched and executed.

If both an external interrupt and a timer interrupt are pending at the end

of an instruction execution, the external interrupt is serviced first. The

SWI is executed the same as any other instruction, regardless of the I-bit

state.

Table 4-1. Vector Address for Interrupts and Reset

Flag

Name

Interrupts

CPU

Interrupt

Vector

Address

N/A

Reset

RESET

$1FFE–$1FFF

N/A

Software

SWI

$1FFC–$1FFD

N/A

External Interrupt

IRQ

$1FFA–$1FFB

TCSR

TOF

Timer Overﬂow

TIMER

$1FF8–$1FF9

N/A

RTIF

Real-Time Interrupt

TIMER

$1FF8–$1FF9

CPICSR

CPIF

Custom Periodic Interrupt

CPI

$1FF6–$1FF7

SSR

Synchronous Serial Interrupt

SSI

$1FF4–$1FF5

MSR

MIF

M-Bus Interrupt

M Bus

$1FF2–$1FF3

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 34 Page - NXP Semiconductors

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