HC705E5GRSSLASHD datasheet(88/148 Pages) NXP

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Motorola Bus (M Bus) Interface

General Release Specification

MC68HC705E5 — Rev. 1.0

Motorola Bus (M Bus) Interface

11.7 M-Bus Pin Configuration

When the M-bus interface is enabled with the MEN bit and the MMUX bit

in the M-bus control register (MCR), the port B data direction register bits

6 and 7 relinquish control to the M-bus control register bits. Enabling the

M-bus does not alter the state of the port B DDR bits.

11.8 Programming Considerations

Programming considerations are discussed in the following subsections.

11.8.1 Initialization

Initialization is accomplished using the following steps:

1. Update frequency divider register (MFDR) to select an SCL

frequency.

2. Update M-bus address register (MADR) to define its own slave

address.

3. Set MEN bit of the M-bus control register (MCR) to enable the

M-bus interface system and set the MMUX bit to allow M-bus

control of the PB7 and PB6 pins.

4. Modify the M-bus control register (MCR) bits to select

master/slave mode, transmit/receive mode, interrupt enable, or

not.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 88 Page - NXP Semiconductors