HC705E5GRSSLASHD datasheet(23/148 Pages) NXP

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General Description

Functional Pin Description

MC68HC705E5 — Rev. 1.0

General Release Specification

General Description

1.5.4 RESET

This active low pin is used to reset the MCU to a known startup state by

pulling RESET low. The RESET pin contains an internal Schmitt trigger

as part of its input to improve noise immunity. See Section 5. Resets for

additional information.

1.5.5 PA0–PA7

These eight I/O lines comprise port A. The state of any pin is software

programmable and all port A lines are configured as input during

power-on or reset. See 7.6 Input/Output Programming for additional

information.

1.5.6 PB0–PB7

These eight I/O lines comprise port B. The state of any pin is software

programmable and all port B lines are configured as input during

power-on or reset. PB7 (SCL) and PB6 (SDA) can be configured as an

M-bus interface. (Refer to Section 11. Motorola Bus (M Bus) Interface

for M-bus pin configurations). PB3–PB5 (TIPL, SCK, and SDIO) can be

configured as a synchronous serial interface (SSI). Refer to Section 12.

Synchronous Serial Interface (SSI) and to 7.6 Input/Output

Programming for additional information.

1.5.7 PC0–PC3

These four I/O lines comprise port C. The state of any pin is software

programmable and all port C lines are configured as input during

power-on or reset. 7.6 Input/Output Programming for additional

information.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 23 Page - NXP Semiconductors