HC705E5GRSSLASHD datasheet(68/148 Pages) NXP

68 / 148 page

Computer Operating Properly (COP) Watchdog

General Release Specification

MC68HC705E5 — Rev. 1.0

Computer Operating Properly (COP) Watchdog

10.3 System Control and Status Register

The SCSR is a read/write register containing the control flags for the

COP rate, COP inhibit, and IRQ level and status flags indicating the

cause of the last reset. Figure 10-1 shows the value of each bit in the

SCSR when coming out of reset.

NOTE:

The debounce time for the IRQ input must be shorter than the COP

timeout period.

STOPR — Illegal STOP Instruction Reset

STOPR is a read-only status bit. This bit is set by the execution of a

STOP instruction when the STOP instruction option is disabled. This

bit is cleared by POR, external reset, or COP reset.

1 = Last reset was the execution of a disabled STOP instruction.

0 = Last reset was not the execution of a disabled STOP

instruction.

ILADR — Illegal Address Reset

ILADR is a read-only status bit. This bit is set by an ILADR reset, but

is cleared by POR, external reset, or COP reset.

1 = Last reset was an ILADR reset.

0 = Last reset was not an ILADR reset.

Address:

$0013

Bit 7

654321

Bit 0

Read:

STOPR

ILADR

COPR

CRS1

CRS0

Write:

Reset:

R = Determined by cause of previous reset

Figure 10-1. System Control and Status Register (SCSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 68 Page - NXP Semiconductors

HC705E5GRS/D Datasheet(HTML) 68 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL