HC705E5GRSSLASHD datasheet(55/148 Pages) NXP

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MC68HC705E5 — Rev. 1.0

General Release Specification

Timer

General Release Specification — MC68HC705E5

Section 8. Timer

8.1 Contents

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.3

Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .57

8.4

Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

8.2 Introduction

The timer for this device is a 15-stage multifunctional ripple counter. The

features include timer overflow, power-on reset (POR), and real-time

interrupt.

As seen in Figure 8-1, the timer is driven by the output of the clock select

circuit (as determined by the value of BCS in the PLLCR) and then a

fixed divide-by-four prescaler. This signal drives an 8-bit ripple counter.

The value of this 8-bit ripple counter can be read by the CPU at any time

by accessing the timer counter register (TCR) at address $09. A timer

overflow function is implemented on the last stage of this counter, giving

a possible interrupt at the rate of fop/1024. Two additional stages

produce the POR function at fop/4064.

This circuit is followed by two more stages, with the resulting clock

(fop/16,384) driving the real-time interrupt circuit. The RTI circuit consists

of three divider stages with a one-of-four selector. The RTI rate selector

bit and the RTI and TOF enable bits and flags are located in the timer

control and status register at location $0008.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 55 Page - NXP Semiconductors